1. Field of the Invention
The present invention relates to a jitter calculating device, a jitter calculating method and a jitter calculating program.
2. Description of Related Art
In recent years, with respect to a semiconductor circuit, a layout design becomes finer, operation speed of the circuit becomes higher and a supply voltage becomes lower. Consequently, a margin is reduced in a timing verification. As a timing constraint becomes more severe, a design is required to be carried out at a higher precision. In particular, due to a voltage drop in a power source Wiring, delays and variations in circuit operations become large. For this reason, a risk of malfunction is elevated due to a fluctuation of a clock signal, which is referred to as a clock jitter. Thus, the magnitude of the clock jitter is desired to be estimated at a high precision.
In designing a semiconductor integrated circuit, a design target circuit is represented by a plurality of cells. Each of the plurality of cells indicates a predetermined element. In estimating a clock jitter, a path as an analysis target is set at first. The set path is a path extending from a clock supply source to a clock supply destination.
The path may include a plurality of cells. That is, a clock signal may be supplied through the plurality of cells to the clock supply destination. A propagation time (delay time) of the clock signal depends on magnitudes of power supply voltages (hereinafter, referred to as supply voltages) which are respectively supplied to the plurality of cells. The supply voltages to the respective cells may change with time. Accordingly, the delay time may change with time due to the changes in the supply voltages. Hence, it is considered to estimate the clock jitter based on magnitudes of changes in the supply voltages.
As related art, Japanese Patent Publication (JP-P2006-277557A) discloses a clock jitter calculating device. The clock jitter calculating device contains: supply voltage analyzing means for calculating changes in power source supply voltages to respective cells included in a propagation route of a clock signal in a predetermined time interval; delay time change calculating means for calculating changes in delay times for the above respective cells, which correspond to the above changes in the supply voltages; and jitter calculating means for calculating a magnitude of a jitter of a clock signal transmitted through the propagation route based on the above changes in delay times.
Also, as another related art, Japanese Patent Publication (JP-P2000-305966A) discloses a delay information generating (system. Japanese Patent Publication (JP-P2000-305966A) discloses that cell delays in all paths of other input cells are obtained by using an effective load capability and a rise or fall time of input waveform as keys.
By the way, the magnitude of the clock jitter does not depend on only the change in the supply voltage. The delay time in each cell also depends on a transition time of a clock signal (input signal) supplied to the cell. Also, a clock signal (output signal) outputted by each cell is supplied as an input signal to a cell arranged in a lower stage of the cell. Here, in each cell, the transition time of the output signal depends on the transition time of the input signal. Thus, the transition time of the clock signal successively changes at every passing a cell. Hence, the degrees of the influences of the transition times of the input signals on the delay times in the respective cells successively change.
Also, the transition time of the clock signal (output signal) outputted by each cell is also based on the magnitude of the supply voltage to the cell.
The present inventor has recognized as follows. In Japanese Patent. Publication (JP-P2006-277557A) and Japanese Patent Publication (JP-P2000-305966A), it is not considered that the delay time in each cell depends on the waveform of the input signal. Furthermore, it is not considered that the transition time of the output signal from each cell depends on the supply voltage. Therefore, there is a problem that a jitter cannot be estimated accurately by the method disclosed in Japanese Patent Publication (JP-P2006-277557A) or Japanese Patent Publication (JP-P2000-305966A).